Apple Chip Architecture from 1977 to 2026
This is a dual-purpose post. On the face of it, I’m covering the various chip architectures employed by Apple over the last 50 years, colouring in the technical considerations and the business context. But, much like I mix my cats’ worm treatment into their food, I am sneakily grinding healthy chunks of learning into the prose: each chapter serves as a framing device for fundamental CPU concepts, growing in complexity. If Android is more your cup of tea, just jump between chapters at will like an overclocked instruction pointer. Sponsored LinkAI paywall editor: build your paywall by just prompting
ContentsClick any of these to skip the intros and start learning. 1977: 6502 Microprocessor and the Apple I & ][ 1984: Motorola 68k and the Macintosh 2006: Intel x86 and the MacBook 2020: Apple Silicon and disruptively good laptops Apple’s core counter-positioning has been firm from their founding all the way to becoming a $4T megacorp: tight integration of hardware and software. This gives them pricing power that OS players (Microsoft, Google) or hardware manufacturers (HP, Dell, Samsung) only dream of. Maintaining this integration gives them a durable competitive advantage. It allows them to make products that “just work”, and also gives them full control over the ecosystem (ask Meta if that matters). This control is what allows them to casually migrate their entire chip architecture. They’ve done it three times! There’s often skepticism regarding CPU architecture migrations. Devs get tetchy about you deprecating all their software at once.
With 2005’s move to Intel x86, some commentators even guessed it was a precursor to bringing Apple onto Windows. The horror. But, ultimately, Apple has their reasons: short-term pain for strategic gain. Each new CPU architecture helped Apple compete and differentiate. Today’s odyssey goes through the 5 key eras of Apple CPU architecture. 1977 up to 2026. I’ll colour in the business context surrounding each migration and bring you forward through the results of each shift. Along the way, we’ll learn the basics of CPU technology; learning increasingly complex chip design techniques along the relentless learning curve of technological advancement. This post is full of knowledge, so much so that your email client might cut it off. Read on my website for the best experience. 1977Chip Family: 6502 microprocessor
1 smelly hippy. 1 big bushy beard. It can only be the 2 Steves. The Apple I in 1976 launched the company. If you can dust off one of the 200 units ever produced, you’re in luck as it’s the most valuable personal computer in the world (think Ferrari money). The Apple ][ (pronounced “Apple Two”) was their first smash hit, so good they milked it for 16 years. It truly helped revolutionise the personal computing, uh, revolution. In the mid-70s, hobbyists orbited a few popular microprocessors like the Intel 8080 and the Motorola 6800. The instruction set architectures of these chip families were the closest thing the nascent world of hobby computing had to an ecosystem. A few Motorola engineers defected to MOS Technology to build the 6502, which was similar enough to 6800 for Woz to be familiar with it (maybe too similar: MOS flew too close to the sun with the 6501 and got sued for IP theft). The Intel 8080 and the Motorola 6800 both cost more than $150, which is approximately a fucktillion in 2026 dollars. Therefore the choice of 6502 was not so much strategic and more because it cost $25, and Woz’s stock options had not yet appreciated that much. He was able to cheaply acquire a bunch of 6502s, cobble together some computers, and write a BASIC interpreter. BASIC was the “vibe coding” of the day. Hardcore, gruff, staff-engineer archetypes have always looked down on people not doing “proper programming” (6502 assembly) and relying on words instead. Woz aptly performed the 3 core activities of early computer manufacturers: choosing an off-the-shelf processor, designing hardware around it, and providing a friendly programming environment. These form the foundation of the integration between hardware and software maintained by Apple today. The Apple I was a neat machine that counter-positioned against the do-it-yourself “kits” popular in the day: a pre-built, quality-tested, plug-and-play board introducing the “it just works” philosophy. The Apple ][ took this baseline and created a killer consumer product with colour graphics, sound, a plastic case, expansion slots, and BASIC in its read-only memory. Both used the 6502.
The 6502 was an 8-bit CPU running at 1.023 MHz, with a 64KB memory address space: just a hair more powerful than today’s RyanAir mobile app. OK: numbers, acronyms, words, blah blah blah. Let’s get on the same page. The CPU™A CPU, or central processing unit, is a device that moves data from computer memory (RAM) into fast temporary memory (registers), runs operations on this data, and then moves the output back into memory. A control unit takes a feed of instructions, decoding them one-at-a-time, to decide what data moves to which register, and which register’s data should be piped through which logic circuits. Fundamentally, all software behaves by arranging inputs into the CPU and handling the outputs. Databases. Operating systems. Intelligent refrigerators.
RegistersA register is a tiny speck of storage hardware. When I say “electronic memory,” I mean a circuit which, while powered, is able to hold onto its current value: on or off, 1 or 0. The smaller you can get this circuit, the more data you can store. This is also, more or less, how RAM works (except there’s a lot more of it).
Registers hold a tiny number of bits very close to the CPU processing circuits. They are small, and close, making them really fast, operating at the MHz (or later, GHz) levels of the fully-clocked CPU. The ALUThe last key piece of circuitry to understand is the Arithmetic-Logic Unit (ALU), the aforementioned “logic circuits” that actually perform these operations. The ALU is fundamentally a collection of circuits that perform simple, specialised jobs, such as:
The CPU executes instructions to perform operations on the data in registers, manipulating 1s and 0s which, by the magic of boolean algebra, emerge into useful outputs such as matrix multiplication, collision physics in a video game, or rasterising image data into on-screen pixels. If this section has afflicted you with FOMO, someone built an Apple ][ emulator in JavaScript.
1984Chip family: Motorola 68k
1981. Reagan. MTV. Indiana Jones. The Apple ][ is a cashflow geyser, but there are barbarians at the gates. IBM has finally penetrated the PC mass market, precipitating an unprecedented influx of purchase orders for PCs. A young, brash, 24-year-old whizkid named Bill Gates was asked to supply their operating system.
Apple needed a new platform upon which to build their future. Apple’s Lisa is shaping up to be their flagship product. After being a huge jerk to everybody for 5 years, Steve Jobs has been relegated to run the low-end Macintosh project. Choosing a CPUOriginally planned as a lower-price-tier computer, the Macintosh under Jobs pivoted to focus on one thing: upstaging the Lisa team. Steve got some “inspiration” from his friends at Xerox PARC to bring a cutting-edge GUI to the Macintosh, and demanded advanced hardware to support it. Understanding how a CPU works doesn’t come up every day, but for a lot of software engineers it’s assumed knowledge you have to pick up someday. Apple’s story over 5 decades is also interesting reading. Read ahead for the full set of 3 chip architecture migrations, from Motorola 68k, to PowerPC, to Intel x86, ultimately to Apple Silicon. The full article ships to everyone in a month. Paid members read now, plus: ⚓️ Access my full library of 48 paywalled articles This isn’t the 70s anymore. This is modern warfare: the early 80s. Your CPU choice is existential. It underpins your OS and the entire software ecosystem you want to nurture. 8-bit is old hat. We need a modern 16-bit processor to compete with IBM. You really have 3 choices available: Intel 8088, the Zilog Z8001, or the Motorola 68k. 8-bit vs. 16-bit“Bits” of course refers to 1s and 0s, but bits of what? It depends. 8-bit and 16-bit refer to the “width” of various components like:
A CPU with 8-bit registers, buses, and ALU circuitry can execute a For an address bus, the wires (I think by now it’s etchings) that carry the memory address for any I/O operation, you can’t get far with 8 bits. That encodes 2⁸ different values, or 256 possible memory addresses. Even the hobbyist generation couldn’t really make that work and mostly used 16-bit address buses, offering 2¹⁶ addresses. This yielded the 64KB address space available on the 6502 microprocessor used in the Apple ][. 16-bit is a very broad generalisation, because the chip families in this generation do not line up neatly between registers, buses, and logic circuits. EndiannessEndianness is a major compatibility consideration when picking a chip architecture. Systems are either big-endian or little-endian, which defines the order in which they store bytes. Consider a number encoded in 16 bits: 41,394, in hexadecimal fashion, would be represented in memory as Now that you understand this, I can share what my blog has been building up to for 3 years: my favourite programming meme I ever made.
Assembly LanguageSoftware written for one processor won’t necessarily run on another. Different families of processors naturally contain different instruction sets. This refers to the list of operations that can be performed by the CPU. A compiler, fundamentally, breaks English computer code down into this “assembly code”. Let’s say you want to add two numbers. Here’s how you might do that in each flavour of assembly that Apple was looking at. Endianness and assembly come into play in the next chapter, during the first true architecture migration: Since the instruction sets are different between CPUs, switching chip architecture means all existing software in the ecosystem would need to be re-compiled. If you’re coding a compiler, or generally any code that makes assumptions about endian-ness, you might need to rewrite quite a bit. Are we all on the same page? Let’s get back to Apple. Intel vs Zilog vs MotorolaLet’s imagine you’re Apple’s VP of Hardware presenting to Jobs. Which chip do you reckon you’d pick? Intel 8088
Zilog Z8001
Motorola 68k
Overall, the Motorola 68k appeared to be the forward-thinking choice to show why 1984 won’t be like 1984. The weaker dev ecosystem and compatibility were necessary sacrifices to allow for brand differentiation against the dominant IBM PC. What’s more, the 68k had a (mostly) orthogonal instruction set, meaning most registers worked for most CPU operations. This is a technical but straightforward bonus: devs don’t have to constantly keep your programming guide open for referencing which instructions work on which registers. This makes developing a lot easier, nice for nurturing a nascent software ecosystem. The 16MB addressing range ended up becoming critical: the Macintosh reserved much of the address space for non-negotiables like system software, ROM, expansion ports, I/O… leaving a pithy 4MB of computer memory shared between software applications. If, in 2012, you ever looked, dismayed, at the storage held by iOS in your 16GB iPod Touch, you’ll know that the more things change, the more they stay the same.
With that boring chore out of the way, Apple and the Motorola 68k were good to go for the next 10 years. 1994Chip family: PowerPC
The year is 1994. Steve Jobs was ousted by Apple 9 years ago, and is busy with NeXT and Pixar. Apple is losing relevance. Their former bitter PC rival, IBM, is in the long, painful process of having its lunch eaten by Microsoft.
Intel and Bill Gates, who was more commonly known as “the devil” in the 1990s, had entered an unholy alliance referred to as Wintel, carving out a near-monopoly for both businesses. Intel had just produced the greatest innovation since the transistor: giving their chip a cool name. The Pentium processor powered the Microsoft market-share munching machine. The x86 family boasted 100MHz clock speeds, high performance, unrivalled economies of scale, and the momentum of the Windows ecosystem. The Motorola 68000 chip family that carried the Macintosh into the 90s was failing to keep up. With the computer world under threat from monopoly, Apple joined up with its longtime partner, Motorola, and an unlikely ally, IBM. The plan: use the power of friendship to fight the forces of capitalism. The AIM (Apple, IBM, Motorola) alliance was born. They planned to counter-position themselves against the x86 heavy, backwards-compatible, very legacy CISC architecture. AIM deployed a RISCy tactic: PowerPC. CISC vs. RISCThere are two opposing chip design philosophies:
Each CPU, constrained by the actual physical layout of its circuitry, can perform a limited number of different operations or utilise a specific set of registers. This is their Instruction Set.
The two schools of thought create divergent approaches for designing a CPU: CISC uses a complex instruction set to build tons of functionality into the CPU. You gain the power to perform complex multi-step processing with single instructions, like RISC applies the “keep it simple, stupid!” philosophy. CISC is a pain to develop. Compiler engineers and Rollercoaster Tycoon developers writing CISC assembly had to consult thick reference tomes to look up instructions they might need. RISC devs were laughing with a simpler instruction set cached fresh in their memory. PipeliningYour code is compiled down into machine code, fed into a CPU as a sequence of binary instructions, and executed sequentially. In the previous section, I mentioned the CPU is running operations every clock cycle. Let’s take a closer look. CPUs run the fetch-decode-execute cycle on a loop. In short, in a single clock cycle, one of three things is done:
Interleaving these instructions concurrently is called Pipelining.
With CISC, operations may not be consistent, with some complex multi-step instructions taking 10+ clock cycles to finish. This can make it tough to optimise performance as operations may not line up nicely. On RISC CPUs, operations are more regular, and easier to line up concurrently. This means you can run 3 instructions for the price of one (clock cycle). Executing one, decoding the next, and fetching the one after. This means that, in ideal conditions, ~1 machine code operation executes per clock cycle. Clock SpeedThis is a lot of work to fit more instructions into a clock cycle. The 6502 ran at ~1 MHz in 1977, and by the 2000s, chips easily reached low-single-digit GHz. Why not just sit back and push this number some more? A CPU clock works like a metronome. Between two ticks, an electrical signal must move through a circuit, settle into a valid state, and be captured by a register. Max clock speed is bottlenecked by the slowest path through these circuits. There is an important relationship between the various attributes of an integrated circuit:
In the 70s, 80s, and 90s, Moore’s Law carried the improvement, as the number of transistors on a chip doubled every couple of years. With smaller transistors, capacitance scaled down. A smaller transistor also required drastically less voltage to switch from 0 to 1. On a smaller transistor, the critical path for signals shortens, so frequency can go up. C and V² go down; f goes up; cancelling out to yield a way higher clock speed for the same amount of power. This free lunch was called Dennard scaling. At a certain point, and this point was the early 2000s, V² became a problem at around 1 volt. You can’t lower it forever, because the semiconductor inside a transistor can’t switch reliably below a minimum threshold voltage. Now, you can’t raise frequency much without increasing power, heat, and melting the chip. This is the power wall. That’s why chips still run at low-single-digit GHz. It’s the whole reason that multi-core processors, alongside all these techniques, are all the rage. The PowerPC TransitionApple and the AIM alliance hatched their scheme. PowerPC, a modern RISC microprocessor architecture, was built to compete directly with the dominant Intel x86 architecture. PowerPC promised better efficiency, i.e., more CPU operations per watt of electricity. Because Apple controlled both software and hardware, they could optimise their OS for this processor architecture. Now they just had to migrate their entire developer ecosystem. Apple applied two tactics to smooth this over: An emulator was developed where PowerPC Macs could emulate the 68k CPU. This translated instructions from one instruction set architecture to another in real-time. This, unsurprisingly, incurs a significant performance cost (of about 35%). Fortunately, since the PowerPC CPUs were so much more powerful, emulation wasn’t usually a massive issue for consumers who were upgrading their hardware (recall this is back when people bought one computer a decade, and they got 2x fast every 2 years). Apple also introduced “fat binaries” for the transition period, which frankly doesn’t sound very PC. Picture a CD-ROM containing a program compiled with machine code for both 68k and PowerPC architectures, making it simple to ship on both platforms. In the era when 80MB was a decent hard drive, this was pretty annoying, so a cottage industry of binary stripping tools spawned so end-users only needed to save the one that worked on their device. Overall, Apple’s migration was a success. Moving from 68k to PowerPC lent a massive performance boost. Emulation and fat binaries allowed the developer ecosystem to transition without everything breaking. Unfortunately, the Wintel alliance was barely touched. Their market dominance grew to unprecedented levels with the release of Pentium and Windows 95. Windows grew into the default computing platform, tragically transforming school ICT curriculums the world over into “how to use Microsoft Office”.
Now that they had a solid hardware platform, Apple’s antiquated System 7 Mac OS became the primary headwind. Internal projects to create a modern competitor to Windows had failed, which meant an acquisition was the only way out of a tailspin. Just buy a new OS, bro. This laid the groundwork for Apple’s purchase of NeXT and the return of Steve Jobs. 2006Chip family: Intel x86
By the early 2000s, Apple had its mojo back. The NeXT acquisition may go down in history as the greatest of all time. Yes, it brought back Jobs (actually almost every exec position was hijacked by NeXT alums). Arguably as important, it bought their foundational ecosystem like Objective-C, Cocoa, and Interface Builder, which lay the path to Mac OS X and (ultimately) iOS. They began to crush the consumer electronics market with hits like the iMac and iPod. Desktops dominated the 80s, the 90s, and the turn of the millennium. But as Moore’s Law marches inexorably onwards, electronics are miniaturising, and laptops are becoming big business. When your hardware isn’t connected to mains, battery is the bottleneck. When looking at performance-per-watt, early 2000s PowerPC architecture was just failing to keep pace behind the Intel x86 behemoth. Intel had simply been out-executing, out-manufacturing, and out-R&D-ing the competition. Their vast installed base of Windows hardware granted an unbeatable ecosystem of compatible software, and printed money to further invest in deepening the Intel processor technology moat. This is what I meant earlier when I said economies of scale. WWDC 2005
Jobs explained it best at Apple’s 2005 Worldwide Developer Conference:
The early-2000s PowerPC CPUs used far too much power and generated far too much heat to create the ultra-thin MacBook Air that Apple wanted. With more than half of their Mac revenues already drawn from laptops, the decision was clear: to compete, Apple had to switch to Intel. But my favourite part of the video? “So get on Xcode 2.1 and get your copy today. There will be a copy for everybody at the registration desk immediately following this keynote.” As someone who became a developer in the 2010s, picking up a CD at a conference for your latest Xcode update seems so quaint. I wonder if the 2005 Betas were as glitchy as we are used to today. What made Intel x86 CPUs so much better?I’ve waxed lyrical about economies of scale, but why was x86 actually better than the competition? Intel x86 processors are descended from a family of instruction set architectures pioneered in 1978 with the Intel 8086. Future processors, such as 1982’s Intel 80186 or 2000’s Pentium 4, maintained backwards compatibility with this original instruction set, meaning that (theoretically), machine code compiled for the 8086 in the 70s should run just fine in the 2000s. But a rich software ecosystem is just part of the story. By 2006, high-end x86’s were predicted to yield 5x the performance-per-watt compared to PowerPC. Intel was innovating on all aspects of their CPUs, such as:
Let me make this clear. The next morsels of CPU theory I’m grinding up into your dog biscuits existed for years in prior generations, and all modern chips were doing this. These weren’t x86 trade secrets. But, in chip design, consistent execution and incremental optimisations across all of these interconnected systems (and more) kept Intel ahead of the pack. CPU CachesEarlier, I explained that registers were small, close to the chip, and hence very fast. RAM is big, far away, and slow. But at GHz clock speeds, you sometimes need rapid access to more than a handful of tiny double-digit-bit-register-sized values. CPUs evolved on-chip caches to store these middling amounts of data. These act as intermediary miniature blocks of RAM, stored physically closer to the chip itself, which allow for faster access to the necessary data. These caches, recursively, have their own tiers:
This diagram from Harvard’s CS course explains it a lot better than I ever could:
Whenever a CPU needs to fetch instructions or data that isn’t stored in the nearest cache, it’s known as a cache miss. It needs to check the next tier of cache, or the next tier, or RAM, or disk. This can badly impact speed and efficiency. As a macro-scale analogy, consider how slowly your app appears to load when your program has to look for data over the network, instead of from local storage. Round-trips, even on the nano-scale of a CPU, add up fast. By the mid-2000s, Intel’s x86 CPU caches were ahead of PowerPC, offering fewer round-trips to RAM and better performance. But this isn’t the whole story: caches are worthless unless you have the right data in the right place. Intel invested:
Good CPU caches massively improved performance-per-watt because, when data is next to the processor, less electricity is physically being moved through the CPU’s circuitry as bytes of memory are shunted around. Branch PredictionBranch Prediction sounds like arcane, occult magick when you first hear about it. Branch instructions are the assembly code versions of conditional statements such as This is done with hardware algorithms built directly into the circuits of the CPU. A buffer called the branch history table caches recent branch outcomes, and patterns are analysed to draw predictions. Advanced branch predictors apply the ultimate YOLO method: speculative execution, where instructions on the predicted branch are executed before the outcome is confirmed. Intel’s silicon crystal balls helped the x86 processor go far faster than non-psychic CPUs. Superscalar ArchitectureSuperscalar architecture is parallelism for chips. Superscalar CPUs can simultaneously execute multiple instructions during a single clock cycle:
This architecture works because operations such as arithmetic, moving memory between registers, resolving branches, and floating-point operations require different pieces of circuitry on the chip. Therefore, if you’re smart about it, several instructions can be performed in parallel. This is hard to get right. Contention bottlenecks occur if multiple simultaneous operations need to use the same resource such as a register or an addition circuit. Dependency issues, like one instruction waiting for the result of another operation, can also cause stalls Intel had the will and, more importantly, the R&D dollars, to get superscalar architecture working nicely on their x86 CPUs. Further Intel InnovationsAs well as improvements to caching, branch prediction, and superscalar architecture, Intel’s x86 chips optimised many features of their CPUs:
Apple’s Intel Migration StrategyApple again employed their time-honoured transition techniques for a smooth CPU architecture migration. Dropping the Power but now very PC, Apple introduced “universal binaries”.
Apple also introduced Rosetta, a dynamic binary translator in Mac OS X Tiger, the first OS released on x86 Macs, and allowed PowerPC apps to run on x86 automagically. Apple went very far out of their way to explain that Rosetta was not an emulator like its 68k to PowerPC predecessor. It translated application code into x86 on-the-fly while calling into Mac OS X frameworks natively. Apple under-promised with a years-long transition timeline and over-delivered ahead of schedule, shipping tiny form factors and bringing the Mac chips into the modern era. 2020Chip family: Apple Silicon
Anyone who’s read Walter Isaacson’s biography of Jobs will be sick of hearing that tight integration of hardware and software is the core counter-positioning Apple has maintained since the original Macintosh. Reliance on Intel x86 created a strict dependency on Intel’s supply chain, sometimes manifesting as release delays impacting the product roadmap. For decades, chip design was the one that got away. From the off-the-shelf MOS 6502 microprocessor of the Apple I to the high-end Intel Xeon from the 2019 Mac Pro, Apple never truly owned this part of the value chain. But now, they could. The O.G. 2.G. iPhone released in 2007 with a Samsung S5L8900 ARM CPU (Intel got close, but got their sales projections off by 100x). From 2010 onwards, Apple designed its own chips, starting with the A4 in the iPad. Apple iterated. And continued to iterate. 2020. The iPhone is the god of all cash cows. Apple, the most valuable company on the planet (at the time), is plowing $20,000,000,000 of free cash flow into R&D like it’s nothing. The seriously long-termHol’ up. Before we get to the present day, I need to take you back in time. Way back. ARM’s RISC instruction set and chip designs are pretty dominant today. ARM, a.k.a. Advanced RISC Machines, was in fact founded in 1990 as a joint venture between Apple, VLSI Technology, and Acorn Computers. Legend has it… and by legend I mean this unsourced claim on Quora… that Steve Jobs was the one who convinced Acorn to abandon their hardware products and focus on low-power processor design. Jobs wasn’t even working at Apple at the time, but listen… I want to believe it. 5D chess brah. The real story behind ARM’s low power consumption is actually even better. Fast forward to 2008, and the nascent smartphone market was being disrupted again by Android, the new kid on the block. Owning mobile chip designs would give Apple a way to differentiate iPhone even further from their competition (like Samsung, their own supplier) in the newly crowded market. Apple snapped up P.A. Semi for $278m, a fabless (that means it didn’t manufacture its own chips) chip design house known for low-power processors. P.A.’s CPUs were originally based on IBM’s Power architecture, building on a foundation set introduced by the AIM way back in the PowerPC days. The acquisition also meant Apple could indulge in its most burningly intense instincts of hush-hush in-house secrecy, jealously guarding its designs in-house. In 2018 Apple dropped $600m in a deal with Dialog, a European chip designer, to borrow specialised capability in power-management chips. Apple Silicon and DisruptionApple was iterating on the ARM chips in the iPhone and iPad for years. Mobile consumers are very tetchy about gigantic cooling fans in their pockets, so power consumption and heat efficiency are the big concerns. ARM’s low-power RISC ecosystem was a better fit, supplanting the x86 behemoth for mobile use cases. Once 2020 rolls along, these ARM CPUs were improving fast. Way faster than Intel’s x86 chips.
This isn’t just a case of “Apple super smort”. Intel had been struggling for a long time to scale up new, smaller process nodes. TSMC was eating their lunch when it came to fabricating the most advanced chips. Apple happily sits at the top of the queue when it comes to paying their friends in Taiwan for capacity on 5nm chip manufacturing (and beyond).
By 2020, there was no question. Apple’s ARM chips were good enough for laptops. Apple announced their third big CPU architecture transition with the Apple Silicon and the M1.
What exactly is an M1?The “M family” of Apple Silicon chips are their custom hardware for Mac laptops, desktops, and even modern iPads (as opposed to the A series used on the iPhone). M1 through to today’s M5 Max are referred to as system-on-a-chip (SoC). This is an approach to hardware that differs from the off-the-shelf approach on a desktop PC. Instead of mounting interchangeable components on a motherboard (CPU, memory, graphics card), SoCs integrate the important stuff into one component. This lends itself naturally to space-constrained mobile devices. I remember when my first startup got a small angel investment in early 2021. I successfully petitioned my commercial cofounder that I would get more done with a shiny new M1 rather than the stinky second-hand i7.
That first-time experience was magic. Lightning-fast boot time, the cooling fan never protests, and the battery somehow lasts all day on a single charge. So how was the M1 so powerful, when using so little power? Apple’s not-so-secret sauceAs mentioned before, the interconnected nature of a CPU makes it impossible to point to one concept and say “this is why Apple is kicking Intel’s arse”. Frankly, the biggest factor is probably Apple’s extremely deep pockets allowing them to call dibs on TSMC’s most cutting-edge fabrication capacity before anyone else, while Intel stumbled with constant delays in shrinking their transistors. But that truth does not a compelling article make. I’m going to mash up some more modern chip design techniques and cavalierly claim that I’ve explained Apple’s secret sauce to you. Heterogeneous ComputingApple Silicon’s secret sauce is their heterogeneous computing strategy. Specialised components for specific workloads. PC gamers will know what I’m talking about: before it became a $4T beast, Nvidia was peddling GPUs designed to handle the specialised parallel workloads encountered by videogame graphics. An ordinary microprocessor from 1977 has different circuits specialised for specific machine code instructions: boolean logic, moving values between registers, performing arithmetic. The original M1 SoC goes up a level of abstraction, with different subsystems on the chip specialised for broad categories of computing task:
Apple Silicon uses ARM’s big.LITTLE approach, using twin sets of CPUs to optimise power consumption for general computing workloads (those that aren’t dispatched to specialised components). The Firestorm CPUs relentlessly execute time-sensitive workloads requested by the user; while the Icestorms handle less urgent work more slowly while consuming 90% less power. Unified Memory ArchitectureThe M series uses a unified memory architecture shared between GPUs and CPUs. Ordinarily, when sending data to the GPU for processing, a CPU usually has to copy data into GPU’s own memory before it can be read. Caches? Storage? What’s that? This isn’t that easy, or everyone would use integrated graphics:
Apple’s approach allocates a shared pool of memory between both CPU and GPU. They cooked it with the mouthfeel of big chunks for the GPU, with that high throughput flavour enjoyed by the CPU. ARM chips are low-energy enough to integrate on the same die without melting a hole through your lap(top). Out-of-order ExecutionWhile the heterogeneous architecture allows specialised workloads to go to the best tool for the job, the Firestorm CPU cores themselves are pretty beastly for general workloads. Old-school CPUs execute instructions one by one, in order, from a stream of machine code. Superscalar CPUs simultaneously fetch, decode, and dispatch multiple instructions at once. The M-series go even further with out-of-order execution: “who cares what order these instructions are in, let’s just utilise as much of our registers and execution units as possible”. The ARM A64 instruction set helps with this: instructions are consistently 4 bytes, as opposed to the 1-15 bytes in x86. This means the incoming stream of machine code instructions can be blasted straight to decoders without boundary decoding overhead. Each performance core has 8 decoders, which the cores fill simultaneously each clock cycle, yielding optimised utilisation of all its circuitry. Apple Silicon analyses a dependency graph between hundreds of instructions at once, so it knows what can be dispatched now, and what needs to wait on results. Pair this with advanced branch prediction, and we’re off to the races. Physics: The Ultimate ConstraintThere is another big reason the M series is so powerful for its efficiency. It’s the same concept we looked at when discussing CPU caches. Simply put, everything on the SoC is physically so close together. With electrical signals moving at a finite speed*, data moves faster when there is less distance to travel.
Apple’s Final Transition?Apple continued to apply its battle-tested approach for the transition from Intel x86 to Apple Silicon. Developers can ship universal apps containing both Intel and Apple Silicon binaries. Rosetta was upgraded to invisibly interpret Intel instructions into ARM on-the-fly. It was a painful blow to Intel for one of their biggest customers to break off their longstanding partnership. Intel began its journey through the five stages of grief and is starting to recover their mojo.
After being complacent for too long, Apple Silicon might have been the kick up the arse they needed to get their ship in order.
Last OrdersEverybody rightly takes the piss out of Apple for their apparent total failure (so far) when it comes to AI, but I reckon they will have the last laugh, and it’s all down to Apple Silicon. Open-weight models are about a year behind the frontier labs. As DeepSeek has proven, it’s possible to get excellent results from distilled local models. When local inference hits the GPT-5 level, distribution will rear its ugly head as the ultimate moat, as it always does. Who owns an enormous install base of hundreds of millions of advanced neural engines, GPUs in a SoC, and personal context? Equally important: which company has spent decades earning customer trust with their privacy? Just one I can think of. I started writing this post in 2023 as a brief history of Apple’s famous CPU architecture migrations. This 2026 edition is a full re-write with a lot more detail, and the missing 6502-era Apple ][ section added. My curiosity kind of got away from me. I was frustrated with the surface-level depth of most sources.
I hope you learned a little, and most importantly, had some fun on the way. Sponsored LinkAI paywall editor: build your paywall by just prompting
If you enjoyed my post, subscribe free to join 100,000 senior Swift devs learning advanced concurrency, SwiftUI, and iOS performance for 10 minutes a week. Paid members get a lot more: ๐ Access Elite Hacks, my exclusive advanced content
Sent from my iPhone
|
